Building a RISC-V CPU Core (LFD111x) Course Overview

Building a RISC-V CPU Core (LFD111x) Course Overview

This is a crash course in digital logic design and basic CPU microarchitecture. Using the Makerchip online integrated development environment (IDE), you will implement everything from logic gates to a simple, but complete, RISC-V CPU core. You will be amazed by what you can do using freely-available online tools for open source development. You will familiarize yourself with a number of emerging technologies supporting an open-source hardware ecosystem, including RISC-V, Transaction-Level Verilog, and the online Makerchip IDE.

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  • Live Training (Duration : 8 Hours)
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  • Classroom Training fee on request

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You can request classroom training in any city on any date by Requesting More Information

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Course Prerequisites

Prerequisites for Building a RISC-V CPU Core (LFD111x)

  • Technical Inclination: A keen interest in technology and a logical mindset will help you engage with the content effectively.
  • No Prior Digital Logic Design Knowledge Required: This course is designed to be accessible, even if you have no background in digital logic design.

This course is structured to guide you through every step, ensuring you grasp all essential concepts and techniques to successfully build a RISC-V CPU core from scratch, using modern open-source tools and methodologies—all from your browser.


Target Audience for Building a RISC-V CPU Core (LFD111x)

Building a RISC-V CPU Core (LFD111x) is a comprehensive one-day course designed for individuals with a technical inclination and no prior experience in digital logic design, focusing on creating a RISC-V CPU using open-source tools.


  • Electrical Engineers
  • Computer Engineers
  • FPGA Developers
  • Embedded Systems Developers
  • Computer Science Students
  • IT Technicians
  • Hobbyists and Makers with a technical interest
  • Hardware Design Enthusiasts
  • Digital Circuit Design Learners
  • Software Developers looking to understand hardware
  • University Engineering Faculty and Instructors
  • Technology Enthusiasts interested in RISC-V architecture
  • System-on-Chip (SoC) Designers
  • Research Scientists in Computer Architecture
  • Technical Managers overseeing hardware development teams


Learning Objectives - What you will Learn in this Building a RISC-V CPU Core (LFD111x)?

Course Introduction

The "Building a RISC-V CPU Core (LFD111x)" course equips students with the knowledge to create a RISC-V CPU using modern open-source circuit design tools and methodologies, all from within a browser. No prior experience in digital logic design is required.

Learning Objectives and Outcomes

  • Understand the fundamentals of digital logic design.
  • Navigate and utilize the online learning platform effectively.
  • Gain insights into the role and significance of the RISC-V architecture in modern computing.
  • Learn the basics of creating a subset RISC-V CPU.
  • Develop and complete a functional RISC-V CPU core.
  • Explore open-source tools and methodologies for circuit design.
  • Apply theoretical concepts in practical, hands-on projects.
  • Comprehend the microarchitecture of a RISC-V CPU.
  • Collaborate with others using modern browser-based tools.
  • Understand the broader implications and applications of RISC-V in the industry.

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